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2023 IISW: The STMicroelectronics Research Team Proposes an Optimized Diode Structure and Pixel Circuits for a Dense, Low-Power 3D-Stacked SPAD


  1. A 10.17μm pitch 3D-stacked SPAD with backside illumination is presented using a 40nm CMOS process.
  2. The technology achieves state-of-the-art 940nm PDE of 18.5% along with low 70fC per pulse power consumption.
  3. A max count rate of 85Mcps is demonstrated, significantly reducing pressure on pixel scaling for high illumination applications.
  4. Temperature stable performance from -20°C to 80°C is shown, with PDE, jitter, speed, and power remaining nearly constant.
  5. The optimized diode structure and novel pixel circuits represent a major advance for dense, low power, high performance SPAD arrays.
  6. This work demonstrates an effective 3D integration and pixel design solution to continue scaling of SPAD technology for applications like LIDAR and imaging.


Single photon avalanche diodes (SPADs) are critical for applications like time-of-flight imaging and Lidar. 3D stacking technology enables smaller, more sensitive SPAD devices with lower power consumption, making them ideal for portable applications. This work presents a 10.17μm pitch 3D-stacked backside illuminated SPAD using 40nm CMOS process. The stack combines a custom top tier optimized for optics with a dense, low power 40nm bottom tier for processing. Novel pixel circuits are designed for low power and high speed operation necessary for continued SPAD scaling.


The backside illuminated design provides a 10x increase in near-infrared sensitivity over previous front-side devices. The optimized surface texturing further enhances absorption 4x, resulting in a high photon detection efficiency (PDE) of 18.5% at 940nm wavelength.
  This is enabled by the vertical diode architecture which achieves a low breakdown voltage (VBD) of 18.6V at 60°C and minimal charge per pulse (CPP) of 70fC, dramatically reducing power consumption.
  The novel pixel circuit allows demonstration of a fast maximum count rate (MCR) of 85Mcps with only 2.5V excess bias, decreasing the need for smaller pixels.
  Remarkably, the performance remains stable from -20°C to 80°C, with the PDE, jitter (119ps FWHM), speed, and power varying less than 15%.
  By implementing 3D integration and customizing the optics, doping, and circuits, this work accomplishes state-of-the-art sensitivity and noise along with breakthrough speed and power metrics.


3D stacking technology

  • Custom top tier imaging process optimized for optics

  • 40nm bottom tier for dense, low power processing

  • Wafer bonding to join tiers

Backside processing

  • Surface texturing and anti-reflective coatings

  • Trench-like shapes for increased optical path length

  • 3D-FDTD simulations to optimize patterns

Avalanche diode design

  • Vertical N+ over PWell junction with optimized doping

  • Full depletion of 4.5μm substrate at breakdown voltage

  • P-doped guard ring to prevent edge breakdown

Pixel circuit design

  • Quenching and detection on high voltage cathode node

  • Highly resistive quenching resistor to limit power

  • AC-coupled detector through MOM capacitor

  • Fast inverter pulse shaping

  • Cascode transistors for pixel disabling


  • Photon detection efficiency vs wavelength

  • Dark count rate, jitter measurements

  • Light count rate for maximum count rate

  • Temperature dependence

Comparison to state-of-the-art pixel performance


The optimized 3D stacked technology and novel pixel circuitry in this work represent a major advance for SPAD arrays. The high sensitivity, low power, and high speed will benefit applications like LIDAR and portable imaging.Further scaling of dense, low power SPAD arrays is essential for progress in single photon detection. This work demonstrates an effective solution using 3D integration and optimized pixel design.

Fig. 1. Cross-section of our 3D-stacked backside illuminated SPAD pixel.

Fig. 4. Photon Detection Efficiency vs wavelength and excess bias at 60°C.

Fig. 8. Light Count Rate (LCR) measurement vs excess bias at 60°C. Max
Count Rate (MCR) values correspond to the peak of each LCR curve.