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EPFL & TSMC Collaborate to Create a 45nm CMOS Single-Photon Amplifier

EPFL & TSMC Collaborate to Create a 45nm CMOS Single-Photon Amplifier, Essential Measurement Performance Parameters to be Mastered!

Single-photon avalanche diodes (SPADs) are devices that can detect very weak light signals by amplifying a single photon into a large current pulse. They are fabricated using standard CMOS technology, which makes them attractive for many applications that require low-cost, high-volume, and easy integration of photodetectors. Some of these applications include LiDAR for autonomous driving, robotics, and gesture recognition, as well as biomedical imaging and diagnosis techniques such as PET, SPECT, FLIM, super-resolution microscopy, NIROT, and Raman spectroscopy [1]–[4]. However, one of the main challenges of SPADs is the low fill factor, which is the ratio of the active area to the total pixel area. The fill factor is limited by the quenching and recharge circuits that are needed to reset the SPAD after each detection event. Moreover, the fill factor decreases when additional functionality such as counting, timestamping, processing, compression, or memory is implemented within each pixel.

One way to improve the fill factor is to use smaller CMOS technology nodes, which allow for higher pixel density and lower power consumption. Figure 1 shows an example of how the fill factor increases from 1% in a 0.8 μm CMOS process to 35% in a 65 nm CMOS process. However, scaling down the CMOS technology also has some drawbacks for SPAD performance, such as higher dark count rate (DCR) and lower photon detection probability (PDP). These effects are caused by the higher doping concentrations that reduce the depletion region width and increase the tunneling currents in the SPAD junction.


Recently, three-dimensional (3D) stacked technology has garnered attention for its potential to significantly enhance performance metrics like fill factor, functionality, timing, power efficiency, and uniformity. This approach involves placing Single-Photon Avalanche Diodes (SPADs) in the top-tier chip, with data processing circuits on the bottom-tier chip, often using more advanced CMOS technology. This architecture offers flexibility for optimizing processes, improving both Dark Count Rate (DCR) and Photon Detection Probability (PDP) through superior SPAD technology and doping optimization. Moreover, employing advanced technology in the bottom tier allows for features like pixel-level digital memory and histogram processing. Additionally, 3D-stacked technology enables smaller pitch, making multi-megapixel SPADs a feasible prospect.

While there have been previous attempts to create 3D-stacked SPADs, they faced limitations. The first successful attempt in standard 130 nm CMOS technology relied on back-illuminated SPADs and wafer-to-wafer bonding. However, performance was hindered by a thick silicon substrate, primarily affecting PDP. More recently, a back-illuminated 3D-stacked SPAD in 65 nm CMOS image sensor (CIS) technology achieved better PDP and broader sensitivity by improving backside thinning and junction depth.
Nonetheless, these solutions still struggle with reduced PDP in the visible range, lack of sensitivity below 450 nm, and a median DCR typically exceeding 250 cps/μm2, even with moderate excess bias voltage.

3D Integrated SPAD

In this paper, we present the world’s first back-illuminated Single-Photon Avalanche Diode (SPAD) fabricated using 45 nm CIS technology, which is 3D-stacked with a 65 nm standard CMOS technology previously discussed in [8]. We provide a comprehensive characterization of this technology and discuss its advantages.

Our SPAD design offers several key benefits. It optimizes fill factor by utilizing a metal-free substrate, enhances Photon Detection Probability (PDP) at shorter wavelengths through the use of an ultra-thin substrate to minimize carrier recombination during backside illumination. Notably, we achieved a Dark Count Rate (DCR) of 55.4 cps/μm2 and a jitter of 107 ps (full width at half maximum) at 2.5 V excess bias voltage, setting new records for a back-illuminated 3D-stacked CMOS technology.

This outstanding performance is the result of meticulously optimized 3D-stacking, precise damage control, improved doping profiles, and a specialized optical stack [9]–[11], guided by thorough TCAD simulations.

To showcase the SPAD’s capabilities, we designed a complete imaging system within the bottom tier, with the potential for further functionality enhancements in future advanced nodes, enabling denser in-pixel operations.

We validate our approach through an array of identical pixels, each comprising a SPAD, quenching and recharge circuitry, and time-resolved components for single-photon timestamping. The SPAD performance remains uniform across the array, while variations in breakdown voltage and PDP are minimized.

Thanks to low dead time, afterpulsing, and crosstalk, image sensors based on this technology are suitable for a wide range of exposures, from photon-flooded to photon-starved scenarios.

In Section II, we delve into the Back-Illuminated 3D-Stacked SPAD technology. This technology involves stacking two wafers face-to-face, allowing the top wafer’s substrate to be thinned down to a few micrometers. The SPAD is built on a P+/Deep N-well (DNW) junction, where the N-well is intentionally omitted to create a wider depletion region, reducing tunneling noise and improving jitter performance, detection efficiency, and spectral range. A P-well (PW) guard ring (GR) is added to prevent premature edge breakdown, enabling higher electric fields in the active region (as depicted in Fig. 3). The SPAD is designed with a 12.5 μm diameter, 2 μm GR, and a 1 μm distance between GR and cathode. These parameters were chosen conservatively for the initial 45 nm attempt, with the aim of achieving functionality rather than maximizing fill factor.

Future generations can optimize parameters to achieve a fill factor greater than 70%. Metal-1 and other metals are designed to cover the entire SPAD active region, reflecting lower-energy photons back into the active region to enhance Photon Detection Probability (PDP) at longer wavelengths.

cross 3D Integrated SPAD

To fully capitalize on the benefits of the back-illuminated 3D-stacked approach, dedicated technology development and optimization are essential. Thinning the top-tier wafer to less than 3 μm is particularly challenging for 300 mm bulk silicon wafer-based technology. This process involves chemical and mechanical etching, with a final thickness tolerance of less than 3% [9]. Additionally, optimization has reduced defects induced by etching, which can hinder SPAD operation, by over tenfold.

3D Integrated SPAD Schematic

The direct 3D connection technology enables a smaller pitch and better 3D connection quality [10]. The impact of these 3D connections has been significantly minimized through further process enhancements [11].

In Section III, we discuss the Simulation and Characterization Results of our back-illuminated 3D-stacked SPAD technology.

A. TCAD Optimization:

  • TCAD simulation is a valuable tool for analyzing SPAD characteristics before fabrication, providing insights into doping profiles, dark current, avalanche breakdown voltage, and electric-field profiles.
  • Fig. 5 illustrates TCAD simulations of SPADs based on different junctions (P+/N-well and P+/DNW) with their corresponding doping profiles, electric fields, and current-voltage characteristics.
  • In deep submicron CMOS technology, SPADs encounter tunneling noise due to higher doping concentrations, which becomes more critical in ultra-deep submicron CMOS technology (<90 nm).
  • To address this, the proposed SPAD intentionally removes the N-well layer at the junction to achieve a larger depletion region of about 1 μm. The DNW-based junction with retrograde doping offers a thicker multiplication region, wider PDP, and lower DCR.
  • Achieving a large depletion region is vital in advanced CMOS technology nodes (<90 nm).
  • The TCAD analysis also compares the P+/N-well junction, commonly used in CIS technology, with the proposed P+/DNW junction. The latter provides a higher breakdown voltage, larger depletion width, and lower dark currents.
  • The PW GR is implemented at the junction edge to expand the photon-sensitive area.


B. Measurement Results:

  • Fig. 6(a) displays micrographs of fabricated SPADs based on the P+/DNW junction with PW GR, while Fig. 6(b) shows one operating above its avalanche breakdown voltage. Light emission during the avalanche multiplication process reveals the effective active area and fill factor, which reaches up to 60.5%.

Micrograph 3D Integrated SPAD
  • The SPAD exhibits very low dark current in the pA range and a breakdown voltage of approximately 28.5 V, closely matching TCAD simulations (Fig. 7).
  • The inset of Fig. 7 displays the breakdown voltage distribution from 128 SPADs, revealing a standard deviation of 0.11 V.

Breakdown Voltage 128SPAD
  • Fig. 8 showcases time-dependent outputs of the SPAD at various excess bias voltages, illustrating exponential behavior due to RC recharge.
  • Despite the high C (capacitance) values resulting from the standalone SPAD setup, a fully integrated implementation is expected to have much lower capacitance.
  • Fig. 8 also presents DCR as a function of excess bias voltage, reaching 55.4 cps/μm2 at a nominal condition of 2.5 V excess bias. This achievement is attributed to defect-minimized technology and the DNW-based junction’s larger depletion region. DCR exhibits a sub-exponential dependence on excess bias voltage, indicating reduced tunneling contribution at higher bias voltages.

DCR Bias Voltage
  • A P+/N-well junction SPAD, fabricated for comparison, displays about 40 times higher DCR than the proposed SPAD (Fig. 7), confirming the expectations from TCAD simulations.
  • Fig. 9 displays a cumulative DCR distribution from 128 SPADs, revealing a small population of noisy SPADs (approximately 4%).

DCR Distribution 128SPAD
  • Temperature-dependent measurements of breakdown voltage and DCR, ranging from -60°C to 60°C, are shown in Fig. 10 and Fig. 11(a). The breakdown voltage increases with temperature due to higher energy requirements for avalanche at elevated temperatures.
  • DCR exhibits high temperature dependence, suggesting that trap-assisted thermal generation is the primary contributor, and cooling could significantly improve DCR performance.
  • Fig. 11(b) presents the Arrhenius plot of DCR, revealing activation energies corresponding to single-level traps introduced by phosphorus ion implantation. This indicates that Shockley-Read-Hall (SRH) thermal generation, or trap-assisted thermal generation, is the primary factor affecting DCR. Removing traps during the ion implantation process can further enhance DCR.

Room Temperature Value
DCR Versus Temperature
F12 PDP Bias Voltages 1.5 V 2.5 V
  • Timing jitter is characterized using time-correlated single-photon counting (TCSPC) with a solid-state laser source. A jitter of 107.7 ps FWHM is achieved at an excess bias voltage of 2.5 V, including contributions from laser jitter (Fig. 13).
  • The SPAD’s small diffusion tail due to the large depletion region results in excellent FW10M and FW1M, making it useful in applications like quantum number generation and quantum communications.
  • Afterpulsing probability is measured at 1.5% and 2.2% at excess bias voltages of 1.5 V and 2.5 V, respectively, with a 100 ns dead time (Fig. 14). These values are likely overestimated due to parasitic capacitance, and afterpulsing is assumed to be negligible in a SPAD sensor array with comparable dead times.
Afterpulsing probability

In Section IV, we provide State-of-the-Art Comparisons and Discussions of our proposed SPAD with other back-illuminated SPADs fabricated in 3D-stacked CMOS technologies.

Figs. 15–18 present comparisons based on normalized DCR, PDP, and jitter parameters. It is important to note that in advanced CMOS technology, SPADs typically face significant tunneling noise due to narrow depletion widths resulting from high doping concentrations.

  • As shown in Fig. 15, the DCR of other SPADs is highly dependent on the excess bias voltage, and their exponential dependence suggests that tunneling dominates their DCRs.
  • In contrast, our proposed SPAD effectively reduces tunneling-assisted DCR thanks to its large depletion region. This results in a modest upward sloping curve and the lowest DCR at the operating condition.

This comparison highlights the advantages of our SPAD technology in achieving lower DCR and demonstrates its suitability for demanding applications in advanced CMOS technology.

DCR comparison
PDP Comparison
Peak PDP Versus Area Normalized
Jitter Comparison

In conclusion, we have successfully introduced and fully characterized the world’s inaugural back-illuminated 3D-stacked SPAD, integrated into the 45 nm CIS technology. This pioneering detector offers substantial advantages over existing technologies. By employing a P+/DNW junction to achieve a broader depletion region and optimizing the guard ring structure and metal-1 light reflector, we have achieved notable improvements in terms of reduced DCR, enhanced PDP with wider spectral coverage, improved jitter performance, and increased fill factor.

Through extensive TCAD simulations, we meticulously pre-optimized the SPAD design, resulting in exceptional performance metrics: a DCR of 55.4cps/μm2, a peak PDP of 31.8% at 600 nm wavelength with substantial sensitivity in both blue and NIR spectra, and timing jitter of 107.7 ps FWHM and 290 ps FW1M at room temperature with a 2.5 V excess bias voltage.

The article uses parameters such as measuring dark count rate (DCR), breakdown voltage (BDV), photon detection probability, jitter, and post-pulse measurement to verify the research results. Enlitech’s SPD2200 can assist in measuring these crucial parameters!

The SPD2200, integrating advanced optical and electrical systems by Enlitech, simplifies sensor testing and analysis. With a user-friendly interface, it streamlines setup, reducing uncertainties in test results, expediting product development cycles, and bolstering competitiveness. Its compact design facilitates rapid integration into original manufacturing lines, reducing R&D costs during SPAD development, enhancing yield, and positioning itself as a vital tool in the race among manufacturers for LiDAR-focused SPAD chip development.

Enlitech’s SPD2200 stands as the pioneering commercial-grade SPD characterization system, specializing in the analysis and testing of crucial SPADs essential for LiDAR advancements. Recently successfully sold to one of the top three global wafer fabs for SPAD. With its offering of Spectral and Time Domain Characterization Modules, it adeptly caters to diverse measurement requirements in dToF module development, allowing adaptable module selection or combined utilization for a comprehensive characterization approach. The detectable parameters encompass a wide spectrum of critical measurements: full-spectrum spectral response (SR, Spectral Responsivity), full-spectrum quantum efficiency (EQE, External Quantum Efficiency), full-spectrum photon detection rate (PDP, Photon Detection Probability), dark counting DCR (Dark Count Rate), and breakdown voltage BDV (Break-Down Voltage). Furthermore, the system performs an in-depth analysis of SPADs’ characteristic parameters, including Jitter, Afterpulsing probability, Diffusion tail, and SNR (Signal-to-Noise Ratio) to ensure a thorough evaluation.