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A briefing decrypts TSMC's 14-year technology development roadmap of BSI Technology with Bulk Si Wafer

Taiwan Semiconductor Manufacturing Company (TSMC) has made remarkable progress in the R&D and application of backside illumination (BSI) image sensor technology. Compared with conventional frontside illumination (FSI) image sensors, BSI technology has advantages like shorter optical path, higher quantum efficiency, and lower color cross-talk, making it very suitable for high resolution image sensors with pixel size smaller than 1.4 um to achieve higher sensitivity.

But as early as in a 2009 TSMC technical briefing, the company already elaborated its process technologies related to backside illumination image sensors. From today’s perspective, that briefing material was precious and validated TSMC’s subsequent development.

BSI technology requires very complex process steps. First the image sensor wafer needs to be chemical mechanically polished for surface planarization to facilitate subsequent wafer bonding. Wafer bonding is a critical step in BSI process and bubble-free bonding must be ensured. TSMC has successfully achieved highly efficient and reliable bubble-free wafer bonding through continuous optimizations of wafer bonder parameter settings, designing bubble detection methodology, reducing particles at bonding interface, etc. The color filter and microlens design also needs delicate optimizations, for example, using different green color filter materials to tune absorption peak for higher quantum efficiency and lower green-to-blue color cross-talk, using gray-tone lithography to enhance microlens focusing capability.

For wafer thinning, TSMC adopts a non-SOI wet etch process scheme with feedback control system to confine wafer thickness uniformity within +/- 0.1 um, avoiding quantum efficiency loss due to thickness variation. Backside ion implantation activation requires pulsed laser anneal technology. By accurately controlling laser energy, TSMC reduced surface roughness and achieved silicon activation uniformity lower than 1.5%. This realizes low sheet resistance while avoiding thermal damage risks.

To verify BSI technology manufacturability, TSMC has made great efforts in reducing defects, improving tool cleanness, optimizing process monitoring, etc. The cycle time of BSI process has been significantly reduced from initial 4.2 days to 1.2 days, and statistical process control of various process indicators is also very satisfactory. Compared with FSI, the quantum efficiency of 1.75 um BSI pixel has increased by 40-60% and cross-talk decreased by 30-80%, proving BSI’s obvious advantages in photoelectric conversion efficiency and low cross-talk.

Packaging of BSI technology is also very critical. TSMC adopts wafer-level packaging schemes and has realized chip-sized packaging for BSI structures, which can not only reduce stress but also considers integrating with TSV technology for further size shrinkage. Furthermore, combining with wafer-level lens technology in the future can enable more compact camera modules.

That technical document fully demonstrated TSMC’s excellent technical capabilities in BSI image sensor key processes, quantum efficiency improvement, cross-talk reduction, manufacturability, and packaging integration. TSMC has not only achieved mass production for 1.75 um and 1.4 um BSI structures, but also made good progress in BSI technology development for smaller pixel sizes, laying the foundation for future ultra-high resolution image sensors. With the increasing demand for higher pixel and better optical performance in consumer electronics, TSMC’s efforts in BSI technology will enable it to maintain a strong competitive edge in the image sensor market.

BSI Si Technology

  • A cost effective thin down approach by using bulk Si wafers with tight Si THK control by feed forward system
  • The robust wafer edge integrity achieved by introducing an edge trimming tool
  • A bonding recipe & setting with bubble free
  • Successfully introduce laser anneal for backside implant activation and crystal defect elimination
  • Implementation of backside metal shield for black level reference
  • Smooth backside Si surface achieved to minimize its impact to image quality (e.g. stripe pattern, etc.)