New technology for backside polishing of silicon wafers in back-illuminated CMOS image sensor processes

A research team composed of engineers from the Institute of Microelectronics Agency for Science in Singapore, Nexgen Wafer Systems in Austria, and GlobalFoundries in Singapore, led by Venkataraman, have developed a new technique for backside polishing of wafers in the process of back-illuminated stacked CMOS image sensors. These image sensors are highly sought after in various applications such as light detection and ranging (LiDAR).

One of the major challenges of these 3D integrated devices is the precise backside polishing of the single-photon avalanche diode (SPAD) wafer, which is stacked with the CMOS wafer. Backside polishing is typically achieved through a combination of back grinding and sensitive wet chemical etching of silicon.

The research team has developed a wet etching process based on customized chemical reagents of HF:HNO3:CH3COOH, which can achieve selective doping up to 90:1 and etching stop in the p+/p silicon transition layer. They have demonstrated the feasibility of thickness variation within 300nm across the entire 300mm wafer. In addition, they have characterized the coloration and surface roughness of the well-known HNA-etched silicon surface, and proposed a wet cone etching method to reduce surface roughness.

This breakthrough was presented at the 73rd Electronic Components and Technology Conference held in Orlando, Florida, USA, from May 30 to June 2, 2023. The paper was accepted on August 3, 2023, and published in IEEE Xplore (https://ieeexplore.ieee.org/abstract/document/10195401). This breakthrough could potentially advance the application of back-illuminated CMOS image sensors in fields such as intelligent driving for automobiles.