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Optimizing Pixel Circuit Design to Explore New Low-Power and High-Resolution SPAD TOF Image Sensors

Since the early research into avalanche multiplication of p-n junctions in the 1960s, the Single Photon Avalanche Diode (SPAD) has become a popular detector element for 3D Time-of-Flight (TOF) Complementary Metal-Oxide-Semiconductor (CMOS) image sensors. SPADs are ideal candidates for high-speed, time-resolved imaging systems due to their shot-noise limited photon detection capability and high temporal resolution. Today, SPAD-based TOF image sensors are widely used in both consumer and industrial applications ranging from biometric identification, automotive Light Detection and Ranging (LiDAR), terrain mapping to medical imaging.

However, the high temporal resolution of the detectors and the desire for high frame rates from the sensors result in high data rates and large power consumption. This issue is exacerbated when the sensors are embedded into handheld battery-powered devices, where power consumption is an even bigger limiting factor. The data rates and power consumption also constrain the maximum sensor resolutions that can be achieved. Therefore, researchers have proposed the idea of utilizing new techniques to reduce the power consumption of SPAD sensors while increasing the resolution.

Specifically, the research team hypothesizes that, compared to digital pixels, analog pixels can achieve smaller pixel size and lower power operation while maintaining high count depth and multi-bin photon detection capabilities. To this end, two key pixel building blocks are optimized: a photon counting circuit based on an analog Charge Transfer Amplifier (CTA), and a two-bin time-gate circuit implemented with a dynamic comparator.

Leveraging these two building blocks, three low-power pixels were designed: a 2-bin and 4-bin pixel with standard source follower readout, and a 2-bin self-referenced pixel with modified readout to remove non-linearity and pixel-to-pixel variation. The pixel sizes range from 4.8 μm to 7.2 μm, including the smallest analog-domain SPAD pixel to date. In addition, a low-swing clock distribution network enabled by the dynamic comparator time-gate is implemented to further reduce power consumption.

Two test chips were fabricated in ST Microelectronics 40nm front-side illuminated CMOS process. The first chip (E4) contains 3×3 test structures for the three different pixel designs. The pixels achieve 7-9 bit multi-bin operation with power consumption as low as 8.6-13.9 nW/MHz SPAD rate. A second test chip (QA8) was fabricated as a 96×64 rolling shutter image sensor for long-range TOF measurements. It implements a 128-bin analog histogram based on CTA and uses a self-referenced ADC. Preliminary results from this sensor architecture are discussed.

In summary, the research team has explored new pathways to enable low-power and high-resolution SPAD-based TOF image sensors through pixel circuit optimization and new architecture designs. This will facilitate the application of TOF technology in wider fields and bring better 3D imaging and sensing capabilities to handheld devices.